FIGURE 2. Block diagram for video switch

I connect the A and B channels to two RGB video cameras that are genlocked together, and connect the output to a video digitizer card in a computer. The PLD is programmed to switch on each field. When I capture a frame, the even field is from one camera and the odd field is from the other. In software I separate these into two images and process them through a stereo correlation algorithm to compute the distance from the cameras to the objects viewed.

Another application would be to take a certain region of the screen from input A part of the time and from input B the rest of the time. This would allow a banner or rectangle from the image A to be overlaid on the image B. The system could also be programmed to switch inputs every few seconds to allow viewing through two cameras or to put the view from the first camera in the top half of the image and from the second in the bottom half so that two cameras could be watched at once.

The ability to generate test patterns can be used to time stamp the video. Basically you generate a test pattern that encodes the frame number as a binary pattern on the image and then you use the switcher to overlay this image onto the left edge of the input video. This is really convenient for finding out exactly how many frames your video capture card is really dropping and whether it ever duplicates frames.

A slight modification of the circuit is required (diode and two resistors) to feed the AC signal into one of the inputs of the PLD so that it can synchronize the output sync signals with the AC line signals. Video cameras can then be genlocked to this input signal, and the video camera captures will synchronize with the flicker of the AC fluorescent lights. This will significantly improve the image in some cases.

Something I have not looked into but am curious about is whether one could regenerate portions of the sync signal that had been corrupted by, say, a video copy protection scheme. It seems like it would be easy just to switch over to the synthesized sync on those scan lines having a corrupted sync signal.

The project is also quite convenient if your scope does not have a TV trigger. Feed a video signal into this device, and then use one of the digital outputs from the PLD as a trigger for your scope. When it comes to video, it slices, it dices; but wait, there's more - it comes with a free TV trigger for your scope.

FIGURE 3. Video signal for a single scan line.

Horizontal Sync

At the start of each scan line, a horizontal sync is transmitted so that the system will know where the scan line starts. This signal is shown in See Horizontal sync signal between two scan lines.. . Here we have a back porch section that is 1.18 m S long at 0.306v, followed by the actual sync pulse that is 4.7 m S long at 0.020v. Finally there is the front porch for 3.14 m S at 0.306v.

Vertical Sync

In addition, the first several scan lines in each field are not used for image data but are used for vertical sync and other purposes. The first three scan lines of the field contain equalizing pulses, followed by three lines of serration pulses, then three more lines of equalizing pulses, as shown in See Vertical sync between two fields.. . The next eleven lines generally contain black scan lines but might have other information such as closed caption. The equalizing pulses are 2.3 m S wide and the serration pulses are 4.7 m S wide.

FIGURE 6. Calculated filter response. This will have a nearly -18 dB effect on the color burst signal while having little effect on the sync signal which is mostly under 500KHz.

 

The various sync signals are fed into the PLD (U8 in the schematic), which can be programmed to select the correct input - more on this later. The PLD is a Xilinx 9536 which is discussed in the Xilinx Data Book See Xilinx, The Programmable Logic Book Data Book (San Jose: Xilinx, 1998).. and Xilinx web page See http://www.xilinix.com. . The PLD also receives a clock signal from the oscillator and controls two LEDs. JP6 allows the logic section to be easily connected up to another circuit or to a logic analyzer. Data lines 0 to 7 can be used as general purpose I/O. Data lines 9 and 10 are pulled to certain logic levels with the resistors R22 and R23. They can be pulled to the opposite levels by putting jumpers on JP6. Digital power is also available on the jumper to power some other circuit, if desired.

The PLD controls U6, the video switch chip. U6 is a Maxim MAX465 See Maxim Max463-470 Two Channel, Triple/Quad RGB Video Switches and Buffers http://www.maxim-ic.com/efp/AllParts.htm. video switch which controls three channels and can select each channel from one of two inputs. It amplifies the signal by a factor of two, which conveniently allows us to divide the signal by two by running it through a 75 ohm resistor before driving the 75 ohm transmission line. This makes it easy to match impedance and to avoid overdriving the output amplifier even if the output line is shorted to ground - something that seems to happen when I build cables. It also double terminates the transmission line, greatly reducing reflections.

The logic block also outputs a two-bit signal into the DAC built by a two resistor network. Resistors R9 and R13 form the DAC for the B input sync while R19 and R20 form the DAC for the output sync. Since the outputs on the PLD can be set to 0, 1, or Z (tri-stated), there are six possible output voltages from this DAC.

The power supply circuitry was designed to keep the noise on the power to the analog chips low. I considered using a switching supply because of concerns about heat dissipation, but I decided the linear power regulator would cause less noise on the video output. The digital circuits have their own supply because this was a simple way to reduce transient noise on the analog lines caused by high speed digital switching. When substituting capacitors or transformers on the input side of the power regulators, keep in mind that a 12v AC transformer means 12 RMS, resulting in a DC voltage of 17v. If the voltage rating of your capacitor is too low, it will fail much sooner than it should.

The input video signal and the associated outputs of the sync detection circuit are shown in See Horizontal sync signals.. . The top trace is the video input for one scan line with a horizontal sync at both ends. The second trace is the field which only changes on a vertical sync. The next trace is the burst which indicates when the color burst signal is active. Finally the bottom trace is the sync, which is active during the horizontal sync.

FIGURE 7. Horizontal sync signals.

 

A longer segment of the signal around a vertical sync is shown in See Vertical sync signals.. . This shows the same signals as See Horizontal sync signals.. but over several lines and a vertical sync. The field changes at the beginning of the vertical pulse.

FIGURE 8. Vertical sync signals.

 

Right now the board uses a mini-din style connector that is similar to an SVideo connector. The advantage of this is that it does not take up much space on the board. The disadvantage is that making cables is a pain. It might have been better just to put a bunch of BNC connectors on the board.

I have designed this circuit such that it should work for NTSC, PAL, and SECAM style video signals, but I have only tested it with NTSC. The only values that deserve much consideration are C11 and R10, which form the time constant for vertical sync detection. The voltage levels generated for output signals by R9, R13 and R19, R20 would also need to be changed.

This project could easily be done using a Cypress ISP PLD or even an AMD Mach ISP PLD instead of the Xilinx.

FIGURE 9. PCB top layer. Note the careful separation of analog and digital signals.

FIGURE 10. PCB bottom layer. Note the ground plane under the whole analog section.

FIGURE 11. PCB component placement

 

Once my board layout was done, I printed it on a laser printer and then carefully checked that all the parts fit their footprints. Putting the paper on a piece of styrofoam and pushing the "through hole" components through the paper is a good way to check the jacks. The easiest way to get the footprints correct is to take some calipers and measure the components. Once I created the Gerber plots and NC drill files, I checked them using GC Preview. This is a great little program for viewing Gerber plot files that you can download See http://www.graphicode.com. . This is an important step: you check that the Gerber output formats are as required by the PCB manufacturer and that the drill files align on top of the Gerber plots.

parts

The first stage of building the board is to order all the components. I tried to select parts that were available from mail order houses such as Digikey See http://www.digikey.com. , Marshall See http://www.marshall.com. , Insight See http://www.insight-electronics.com. , Arrow See http://www.arrowamericas.co. , and Nu Horizons See http://www.nuhorizons.com. . The MAX465 is available from Arrow and Nu Horizons. With the exception of the filter formed by C7, C9 and R3, none of the values are super critical. Even the filter values are not that critical, but play with a SPICE model of the filter before you change them. The data sheet for the LM1881 explains the goals of this filter. In See Part List. I have listed very approximate costs for the components - these could vary widely for low volume purchases. I have also added a flux pen which is very helpful in soldering the QFP.

TABLE 1. Part List

Count	Part	Designator	Footprint	Cost Each
10	0.1uF	C10 C11 C12 C13 C14 C15 C16 C17 C19 C8	1206	0.02
1	0R	R5	1206	0.02
3	10uF 35V	C1 C20 C4	7243	0.37
2	1K	R13 R19	1206	0.02
2	200R	R1 R6	1206	0.02
1	33pF	C7	1206	0.12
2	400R	R20 R9	1206	0.02
1	470pF	C9	1206	0.11
2	470uF 35V	C5 C6	Radial0.2	0.30
2	4K7	R22 R23	1206	0.02
1	619R	R3	1206	0.14
1	680K	R10	1206	0.02
12	75R0	R14 R16 R17 R18 R21 R11 R12 R15 R2 R4 R7 R8	1206	0.11
3	DIN8	J2 J3 J4		2.05
2	DIODE	D1 D2	SMB	0.58
1	HEADER 8X2	JP6	IDC16	0.25
1	JACK	J1 (MODE 3.5MM R/A PC Mount)		0.22
1	LED Green	U3 (IDT 5300H5_		0.63
1	LED Yellow	U4 (IDT 5300H7)		0.63
1	LM1881	U5	SO-8	3.33
1	MAX465	U6	SOL-24	10.79
2	MC7805	U1 U9	TO-220	0.51
1	MC7905	U2	TO-220	0.12
1	OSC-27Mhz	U7	OSC-DIP8	3.47
1	XC9536	U8 (XC9536-15VQ44C(44))	QFP44	4.70
1	PCB	(ordered in quantity 10)		13.00
1	Box	(part number Hammond 1599 B)		3.20
1	Flux Pen	(Kester 450-B-FLU-PEN)		3.80

The next stage is to order the PCB. Gerber and drill plots can be downloaded, or you can generate your own. I ordered the PCB from Alberta Printed Circuits See http://www.apcircuits.com. , who did a nice job. They do not router out the shape of the board, so the first step in construction is to chop out the cutouts on the board with a dremel tool.

Building the board

The completed board is shown in See Completed board. .

esd (Electronic Static Discharge)

A cautionary observation: I've noticed that people with experience in production electronics tend to be careful with ESD. I guess spending several days tracking down an intermittent problem on a chip with ESD damage makes one believe that ESD problems should be avoided. I work on an ESD safe mat that is properly grounded, and I wear a ground strap. The fact that it rains most of the year where I live means that the relative humidity is great for electronics, but if you live in a dry place, take more care. Handling electronics correctly is not hard, so do it right and when something doesn't work, you won't have to wonder if it is an ESD problem. There is plenty of information about ESD on the web See http://www.eosesd.org. and in books See Henry W. Ott, Noise Reduction Techniques in Electronic Systems, 2nd ed. (New York: Wiley, 1988).. .

soldering

One word: flux. It's all easy with flux. Surface mount wasn't designed for hand soldering, but it's easy and quick once you get the hang of it. Very little solder is required; the solder on the board is enough to tack things down.

Let's start with the 1206 resistors and capacitors. The hardest part is holding the component in place while tacking it down. If you have a tweezer solder iron, just put the component on the pad and squeeze the tweezer for a few seconds and release. I use 725°F (385°C). If you don't have a tweezer solder iron, hold the component with tweezers and touch each end with the solder iron. I find a 1/16" chisel tip works well. At this point, we have the component tacked in place but not a good solder. Get the smallest resin core solder you can find and touch the solder iron tip to the PCB and the end of the component, and then feed in a small amount of solder. The goal is a nice concave solder joint, as shown in See Good and bad solder joints for 1206 SMT package. . Easy inspection of the joint really requires a magnifying glass or optical loupe. It is important that everything be clean - use that little sponge by your soldering iron and keep it wet.

VHDL Primer

I am not going to attempt to teach VHDL - get a good book See Stefan Sjoholm and Lennart Lindh, VHDL for Designers (London: Prentice Hall, 1997).. See Keven Skahill, VHDL for Programmable Logic (Reading, MA: Addison-Wesley, 1996).. to really learn it - but I will show you enough things to make you dangerous. As with all programming languages, a not all bad way to learn VHDL is to examine and modify other VHDL programs. In VHDL synthesis, we describe a program that would have the same behavior as the circuit we wish to create. This program is used by the synthesis tools to create the configuration file that will configure the specific FPGA or PLD into a correct circuit. The syntax is very similar to Ada.

The basic building blocks are signals which are virtual wires in a digital circuit. A signal is declared with code something like:

 
signal foo: STD_LOGIC;

To take two signals called A and B and feed them into an AND gate and then assign the output of the AND gate to a signal called C, write code that looks like this:

 
C <= A and B;

Busses of several wires can also be created with a declaration like:

 
signal bar: STD_LOGIC_VECTOR (7 downto 0);

This declares a bus with a seven wires labeled bar(7), bar(6),... bar(0). To AND the first two of these together and assign the result to the signal C, use the following expression:

 
C <= bar(0) and bar(1);

Other VHDL operators include:

logical : and, or, nand, nor, xor, xnor, not

relational: =, /=, <, <=, >, >=

arithmetic: +, -, *, /, rem, mod, abs, **

concatenation: &

The concatenation can be used to combine signals into signal vectors. For example, if we had a bus foo and we wanted to shift it left once into a bus called bar and assign the signal bottom to the bottom bit of bar, we could write something like:

 
signal bar: STD_LOGIC_VECTOR (7 downto 0);

 
signal foo: STD_LOGIC_VECTOR (7 downto 0);

 
signal bottom: STD_LOGIC;

 
bar <= foo(6 downto 0) & bottom;

Another useful construct is the WHEN operator. This allows us to do conditional assignment. Take for example a MUX that combines signals a and b depending on the value of the selection signal s into an output signal called result. The code for this would look like:

 
result <= a when (s = '1') else b;

And Gate Example

Let's look at complete example that creates an AND gate:

 
library IEEE;

 
use IEEE.std_logic_1164.all;

 
library metamor;

 
use metamor.attributes.all;

These lines just include some standard libraries so that things like STD_LOGIC are defined:

 
entity myAndGate is

 
    port (

 
        a: in STD_LOGIC;

 
        b: in STD_LOGIC;

 
        c: out STD_LOGIC

 
    );

 
    attribute pinnum of a: signal is "8";

 
    attribute pinnum of b: signal is "44";

 
    attribute pinnum of c: signal is "7";

 
end myAndGate;

These lines tell the system that we're going to create an entity called myAndGate. One can think of an entity as a virtual chip. This circuit will have two inputs called a and b, and one output called c. The attribute pinnum commands tell the synthesis tool which physical pin number on the PLD to map a virtual wire to. Difference synthesis tools do this in completely different ways, and you will have to figure out how to do it in your tool.

So far we have only told the system that the circuit exists; we have not told it what the circuit does. The following section tells the synthesis tool what the circuit is supposed to do:

 
architecture myAndGate_arch of myAndGate is

 
signal result: std_logic;

 
begin

 
  result <= a and b;

 
  c <= result;

 
end myAndGate_arch;

The result signal is not really necessary. I included it simply to show that more signals can be declared and used in the description of the circuit. This forms a complete example.

Sequential Logic

So I have only described combinatorial logic but have not addressed the issue of sequential logic such as flip flops, counters, and latches. These are described using processes. An example for a D latch would look like:

 
process (GATE, DIN)

 
begin

 
   if GATE='1' then --GATE active High

 
      DOUT <= DIN;

 
   end if;

 
end process;

Here we declare a process that output depends on to input signals called gate and din. Inside of the process we stipulate that when gate is high the value of din will be assigned to dout. When gate is low, we do not specify what is assigned to dout - it is assumed that dout will not change its value when gate is low, regardless of what happens to din:

 
process (GATE, DIN, RESET)

 
begin

 
   if RESET='1' then --RESET active High

 
      DOUT <= '0';

 
   elsif GATE='1' then --GATE active High

 
      DOUT <= DIN;

 
   end if;

 
end process;

We can now create latches. Let's move on to look at clocked circuits such as a D flip flop:

 
process (CLK)

 
begin

 
   if CLK'event and CLK='1' then --CLK rising edge

 
      DOUT <= DIN;

 
   end if;

 
end process;

CLK'event is a special expression that is only true when CLK changes value. On each rising edge of CLK, the value of DIN will be assigned to DOUT.

Next consider a flip flop with asynchronous reset:

 
process (CLK, RESET)

 
begin

 
   if RESET='1' then --asynchronous RESET active High

 
      DOUT <= '0';

 
   elsif (CLK'event and CLK='1') then --CLK rising edge

 
      DOUT <= DIN;

 
   end if;

 
end process;

If we wanted a D flip flop with synchronous reset, the code would look like:

 
process (CLK, RESET)

 
begin

 
   if CLK'event and CLK='1' then --CLK rising edge

 
      if RESET='1' then --synchronous RESET active High

 
         DOUT <= '0';

 
      else

 
         DOUT <= DIN;

 
      end if;

 
   end if;

 
end process;

A slightly more complex example strings 4 D flip flops together to form a 4-bit asynchronous counter:

 
process (CLK, COUNT, RESET)

 
begin

 
   if RESET='1' then

 
      COUNT <= "0000";

 
   else

 
      if CLK'event and CLK='1' then

 
         COUNT(0) <= not COUNT(0);

 
      end if;

 
      if COUNT(0)'event and COUNT(0)='0' then

 
         COUNT(1) <= not COUNT(1);

 
      end if;

 
      if COUNT(1)'event and COUNT(1)='0' then

 
         COUNT(2) <= not COUNT(2);

 
      end if;

 
      if COUNT(2)'event and COUNT(2)='0' then

 
         COUNT(3) <= not COUNT(3);

 
      end if;

 
   end if;

 
end process;  

MORE VHDL

This section shows the complete code for the application to switch on each field:

 
library IEEE;

 
use IEEE.std_logic_1164.all;

 
library metamor;

 
use metamor.attributes.all;

In this section I simply declare all the signals connected to the PLD and set the pin numbers:

 
entity vid_sw_top is

 
    port (

 
        syncNot: in STD_LOGIC;

 
        odd_even: in STD_LOGIC;

 
        burstNot: in STD_LOGIC;

 
       

 
        cs_out_bar: out STD_LOGIC;

 
        sel_out: out STD_LOGIC;

 
        en_out_bar: out STD_LOGIC;

 
       

 
        test: out STD_LOGIC_VECTOR (7 downto 0);

 
       

 
        syncOutA: out std_logic_vector (1 downto 0);      

 
        syncOutB: out std_logic_vector (1 downto 0);       

 
        jumper: in std_logic_vector(1 downto 0);

 
        green: out std_logic;

 
        yellow: out std_logic;

 
       

 
        clk: in std_logic

 
    );

 
   

 
    attribute pinnum of burstNot: signal is "8";

 
    attribute pinnum of syncNot: signal is "44";

 
    attribute pinnum of odd_even: signal is "7";

 
 

 
    attribute pinnum of cs_out_bar: signal is "14";

 
    attribute pinnum of sel_out: signal is "13";

 
    attribute pinnum of en_out_bar: signal is "12";

 
 

 
    attribute pinnum of test: signal is

 
                          "27,29,31,36,28,30,32,33";

 
    attribute pinnum of syncOutA: signal is "6,5";

 
    attribute pinnum of syncOutB: signal is "16,18";

 
 

 
    attribute pinnum of jumper: signal is "22,21";

 
    attribute pinnum of green: signal is "3";

 
    attribute pinnum of yellow: signal is "2";

 
    attribute pinnum of clk: signal is "43";

 
 

 
end vid_sw_top;

 
 

 
architecture vid_sw_top_arch of vid_sw_top is

 
signal vert: std_logic;

 
signal field: std_logic;

 
signal horz: std_logic;

 
signal vertStart: std_logic;

 
signal burst: std_logic;

 
signal sync: std_logic;

 
signal syncGen: std_logic;

 
signal syncOut: std_logic_vector (1 downto 0);

 
signal line:    std_logic_vector (7 downto 0);

 
begin

Here I invert some of the signals and set the fixed outputs:

 
  en_out_bar <= '0';

 
  cs_out_bar <= '0';

 
  field <= odd_even;

 
  sync <= not syncNot;

 
  burst <= not burstNot;

This line sets the output to switch on fields:

 
  sel_out <= field;

If the above line were commented out and the following line commented in, the system would take the first input for scan lines between (binary) 01111111 and 11000000 and the rest of the image from the other input:

 
-- sel_out <= '1' when (( line > "01111111") and (line < "11000000")) else '0';

These lines set the green led to always be on and the yellow led to flash at 30Hz as each field is detected:

 
  green <= '1';

 
  yellow <= field;

Various signals are put out to the test connector so that they can be monitored with a logic analyzer:

 
  test(0) <= sync;

 
  test(1) <= burst;

 
  test(2) <= field;

 
 

 
  test(3) <= horz;

 
  test(4) <= vert;

 
 

 
  test(5) <= '1';

 
  test(6) <= '0';

 
 

 
  test(7) <= clk;

This process detects the vertical sync. It does this by looking at the value of the sync signal during the color burst phase of the sync:

 
process (burst)

 
begin

 
   if burst='0' and burst'event then

 
      vert <= sync;

 
   end if;

 
end process;

This process generates the horizontal sync signal. It is a flip flop that is set whenever there is a sync that is not the vertical sync and is reset on the start of the next burst event:

 
process (burst,sync,vert)

 
begin

 
   if sync='1' and vert='0' then

 
      horz <= '1';

 
   elsif (burst'event and burst='0') then

 
      horz <= '0';

 
   end if;

 
end process;

This process sets the line to the count of the line in the field that we are on. It counts the horizontal sync pulses and uses the vertical sync pulse to reset to zero:

 
process (horz, line, vert)

 
begin

 
   if vert='1' then

 
      line <= (others => '0');

 
   else

 
      if horz'event and horz='1' then

 
         line(0) <= not line(0);

 
      end if;

 
      if line(0)'event and line(0)='0' then

 
         line(1) <= not line(1);

 
      end if;

 
      if line(1)'event and line(1)='0' then

 
         line(2) <= not line(2);

 
      end if;

 
      if line(2)'event and line(2)='0' then

 
         line(3) <= not line(3);

 
      end if;

 
      if line(3)'event and line(3)='0' then

 
         line(4) <= not line(4);

 
      end if;

 
      if line(4)'event and line(4)='0' then

 
         line(5) <= not line(5);

 
      end if;

 
      if line(5)'event and line(5)='0' then

 
         line(6) <= not line(6);

 
      end if;

 
      if line(6)'event and line(6)='0' then

 
         line(7) <= not line(7);

 
      end if;

 
   end if;

 
end process;  

Here the values of the sync out signal are generated. The grey scale value is set depending on which scan line in the field we are at:

 
  syncGen <= (not burst) when (vert='1') else (not sync);

 
 

 
  syncOut(0) <= line(6) when (horz='0' and syncOut(1)='1'

 
                        else syncGen;

 
  syncOut(1) <= line(7) when (horz='0') else '0';

The next section just drives the DAC resistors to the correct values specified by the syncOut signal:

 
syncOutA(1) <= '1' when (syncOut(0) = '1') else '0'; -- 1K

 
syncOutA(0) <= '1' when (syncOut(1) = '1') else 'Z'; -- 402R

 


 
syncOutB(1) <= '1' when (syncOut(0) = '1') else '0'; -- 1K

 
syncOutB(0) <= '1' when (syncOut(1) = '1') else 'Z'; -- 402R

 
 

 
end vid_sw_top_arch;

The PLD equations

All of this stuff gets collapsed into logic equations for PLD by the synthesis tools. The VHDL code from above turns into the following equations:

 
/cs_out_bar = Vcc  

 
/en_out_bar = Vcc   

 
/green = Gnd   

 
/sel_out = /odd_even   

 
/"syncOutA<0>" = Gnd   

 
   "syncOutA<0>".TRST = /"test<3>" * line_7

 
/"syncOutA<1>"  = /"test<3>" */line_6 * line_7

 
       + /burstNot * "test<4>" */line_7

 
       + /syncNot */"test<4>" */line_7

 
       + /burstNot * "test<3>" * "test<4>"

 
       + /syncNot * "test<3>" */"test<4>"   

 
/"syncOutB<0>"  = Gnd   

 
   "syncOutB<0>".TRST = /"test<3>" * line_7

 
/"syncOutB<1>"  = /"test<3>" */line_6 * line_7

 
       + /burstNot * "test<4>" */line_7

 
       + /syncNot */"test<4>" */line_7

 
       + /burstNot * "test<3>" * "test<4>"

 
       + /syncNot * "test<3>" */"test<4>"   

 
/"test<0>"  =  syncNot   

 
/"test<1>"  =  burstNot   

 
/"test<2>"  = /odd_even   

 
/"test<3>" := Vcc   

 
   "test<3>".CLKF =  burstNot

 
   "test<3>".SETF = /syncNot */"test<4>"

 
   "test<3>".PRLD =  GND

 
/"test<4>" :=  syncNot   

 
   "test<4>".CLKF =  burstNot

 
   "test<4>".PRLD =  GND

 
/"test<5>"  = Gnd   

 
/"test<6>"  = Vcc   

 
/"test<7>"  = /clk   

 
/yellow  = /odd_even   

 
/line_0 :=  line_0   

 
   line_0.CLKF =  "test<3>"

 
   line_0.RSTF =  "test<4>"

 
   line_0.PRLD =  GND

 
/line_1 :=  line_1   

 
   line_1.CLKF = /line_0

 
   line_1.RSTF =  "test<4>"

 
   line_1.PRLD =  GND

 
/line_2 :=  line_2   

 
   line_2.CLKF = /line_1

 
   line_2.RSTF =  "test<4>"

 
   line_2.PRLD =  GND

 
/line_3 :=  line_3   

 
   line_3.CLKF = /line_2

 
   line_3.RSTF =  "test<4>"

 
   line_3.PRLD =  GND

 
/line_4 :=  line_4   

 
   line_4.CLKF = /line_3

 
   line_4.RSTF =  "test<4>"

 
   line_4.PRLD =  GND

 
/line_5 :=  line_5   

 
   line_5.CLKF = /line_4

 
   line_5.RSTF =  "test<4>"

 
   line_5.PRLD =  GND

 
/line_6 :=  line_6   

 
   line_6.CLKF = /line_5

 
   line_6.RSTF =  "test<4>"

 
   line_6.PRLD =  GND

 
/line_7 :=  line_7   

 
   line_7.CLKF = /line_6

 
   line_7.RSTF =  "test<4>"

 
   line_7.PRLD = GND

Variations

To switch every N frames, just set up a counter to count even fields and then switch when it hits an appropriate value. Similarly, to switch part way through a scan line, set up a counter that is reset by the horizontal pulse and then counts clock ticks from the oscillator, switching the output when it hits an appropriate value.